This invention relates to a method and an apparatus for controlling a clock signal in a data processing circuit. This invention also relates to a high-speed data processing device.
Some data processing circuits include first and second sections each operating in synchronism with a pair of biphase clock signals. In some cases, the first section completes data processing operation within a period half the period of data processing operation by the second section. In these cases, the first section waits or wastes a time corresponding to a half of the period of data processing operation by the second section. The wait lowers the operation speed of the data processing circuit.